Recently, a renewed interest in thin-film magnetic random access memories (MRAM) has been sparked by the potential application of MRAM to both nonvolatile and volatile memories. FIG. 1A depicts a portion of a conventional MRAM 1. The conventional MRAM includes conventional orthogonal conductor lines 10 and 12, conventional magnetic storage cell having a MTJ 30 and conventional transistor 13. The conventional MRAM 1 utilizes a conventional magnetic tunneling junction (MTJ) stack 30 as a memory cell. Use of a conventional MTJ stack 30 makes it possible to design an MRAM cell with high integration density, high speed, low read power, and soft error rate (SER) immunity. The conductive lines 10 and 12 are used for writing data into the MTJ stack 30. The MTJ stack 30 is located on the intersection of and between conventional conductive lines 10 and 12. Conventional conductive line 10 and line 12 are referred to as the conventional word line 10 and the conventional bit line 12, respectively. The names, however, are interchangeable. Other names, such as row line, column line, digit line, and data line, may also be used.
The conventional MTJ 30 stack primarily includes the free layer 38 with a changeable magnetic vector (not explicitly shown), the pinned layer 34 with a fixed magnetic vector (not explicitly shown), and an insulator 36 in between the two magnetic layers 34 and 38. The insulator 36 typically has a thickness that is low enough to allow tunneling of charge carriers between the magnetic layers 34 and 38. Layer 32 is usually a composite of seed layers and an antiferromagnetic (AFM) layer that is strongly coupled to the pinned magnetic layer. The AFM layer included in the layers 32 is usually Mn alloy, such as IrMn, NiMn, PdMn, PtMn, CrPtMn, and so on. The AFM layer is typically strongly exchanged coupled to the pinned layer 34 to ensure that the magnetic vector of the pinned layer 34 is strongly pinned in a particular direction.
When the magnetic vector of the free layer 38 is aligned with that of the pinned layer 34, the MTJ stack 30 is in a low resistance state. When the magnetic vector of the free layer 38 is antiparallel to that of the pinned layer 34, the MTJ stack 30 is in a high resistance state. Thus, the resistance of the MTJ stack 30 measured across the insulating layer 34 is lower when the magnetic vectors of the layers 34 and 38 are parallel than when the magnetic vectors of the layers 34 and 38 are in opposite directions.
Data is stored in the conventional MTJ stack 30 by applying a magnetic field to the conventional MTJ stack 30. The applied magnetic field has a direction chosen to move the changeable magnetic vector of the free layer 30 to a selected orientation. During writing, the electrical current I1 flowing in the conventional bit line 12 and I2 flowing in the conventional word line 10 yield two magnetic fields on the free layer 38. In response to the magnetic fields generated by the currents I1 and I2, the magnetic vector in free layer 38 is oriented in a particular, stable direction. This direction depends on the direction and amplitude of I1 and I2 and the properties and shape of the free layer 38. Generally, writing a zero (0) requires the direction of either I1 or I2 to be different than when writing a one (1). Typically, the aligned orientation can be designated a logic 1 or 0, while the misaligned orientation is the opposite, i.e., a logic 0 or 1, respectively.
Stored data is read or sensed by passing a current through the conventional MTJ cell from one magnetic layer to the other. During reading, the conventional transistor 13 is turned on and a small tunneling current flows through the conventional MTJ stack 30. The amount of the current flowing through the conventional MTJ stack 30 or the voltage drop across the conventional MTJ stack 30 is measured to determine the state of the memory cell. In some designs, the conventional transistor 13 is replaced by a diode, or completely omitted, with the conventional MTJ stack 30 in direct contact with the conventional word line 10.
FIG. 1B is a high-level flow chart of a conventional method 50 for providing an MTJ stack in a conventional magnetic memory. For clarity, the method 50 is described in the context of the conventional MRAM 1 depicted in FIG. 1A. Referring to FIGS. 1A and 1B, an underlayer, which is part of the layers 32, is deposited, via step 52. The AFM layer that is also included in the layers 32 is deposited, via step 54. As discussed above, the AFM layer is typically Mn alloy, such as IrMn, NiMn, PdMn, PtMn, CrPtMn, and so on. The underlayer is used to achieve a particular type of grain structure and orientation for the AFM layer. Such a grain structure and orientation for the AFM layer allows for a good exchange coupling between the AFM layer and the pinned layer 34 to be achieved.
The remainder of the MTJ stack 30 is deposited, via step 56. In order to activate, align, and strengthen the exchange coupling field, an annealing step is performed, via step 58. When Mn alloys are used in the AFM layer, the annealing step is typically performed at temperatures between two hundred and three hundred degrees Celsius in a magnetic field. The actual annealing temperature is optimized for each type of Mn alloys. If the temperature used in step 58 is too low, the annealing step may not be able to activate the exchange effect or set the direction of the exchange coupling. If the temperature used in step 58 is too high, the annealing step may cause interlayer diffusion of different type of materials and degrade or even damage the exchange coupling.
The MRAM fabrication is completed, via step 60. Step 60 typically includes photolithography and etching processes to define the MTJ stack 30. However, these processes might be performed as part of step 54. In addition, the wafers on which the MRAM 1 is fabricated may still go through some process steps at relatively high temperature.
Although the conventional method 50 and the conventional MRAM 1 function, one of ordinary skill in the art will readily recognize that processing steps performed after fabrication of the MTJ stack 30 may damage the MTJ stack 30. For example, a forming gas annealing step that is used to repair plasma-related damage at the SiO2 and Si interface, is typically performed after step 60. Such a forming gas annealing step is typically performed at four hundred degrees Celsius for thirty minutes. Severe damage may be observed in the MTJ stack 30 after annealing of this type.
Accordingly, what is needed is a method and system for providing a magnetic memory in which performance of the memory element is not compromised due to processing. It would be desirable to achieve reduced interlayer diffusion and/or other damage due to processing without compromising performance of the magnetic element. For example, it would be desirable to obtain a simplified manufacturing process, reduced cell size, improved reliability, improved stability against stray magnetic field, and improved write efficiency. The present invention addresses such a need.